DSPP Application (Patent)

Patent Review

United States Patent US005142164A:  SUBHARMONIC NOISE REDUCTION CIRCUIT

Patent No.: 5,142,164

Inventor: Federico Chu, Des Plaines, Ill.

Review:

                The patent provides a sub-harmonic noise reduction circuit that reduces the signal-to-noise ratio of an electrical circuit having inherent sub harmonic distortion. The invention uses a 2-stage electronic circuit: first stage being a low pass filter and the second, a differential amplifier. The objective of this invention is to provide a sub-harmonic noise reduction circuit that operates with an extended life and relatively low drift when subjected to temperature, humidity or other environmental changes. The circuit is therefore designed to give a reliable DC level output voltage for a given input regardless of the AC distortion which is seen from the graphs. A conventional noise reduction technique requires the use of Fourier Transform which leads to a relatively expensive hardware and/or software as well as excessive power compared to the amplifier circuit of this invention which does not use any complex analysis or hardware, instead using simple time domain analysis.